This invention relates to successive ranged analog/digital converter and in particular to circuits for automatically adjusting for bias errors that are introduced into the analog chain of such devices by the use of high speed amplifiers, hot carrier diode switches and the like.
In a successively ranged analog/digital converter several bits are converted at a time in order to increase the speed over that of a successive approximation analog/digital converter which converts one bit at a time. In the SRADC type of device analog input signals are processed through an analog chain and fed to an n bit parallel analog/digital converter. The analog chain is the portion of the SRADC that determines the maximum operating speed. In order to reduce the propagation time through the analog chain the highest speed amplifiers available are utilized and hot carrier diode switches are used for gain switching. Also the amplifiers are operated over as low an output voltage swing as is feasible. These measures tend to increase bias errors, however. Hot carrier diode switches inherently produce bias errors, high speed amplifiers do not necessarily have good d.c. characteristics and the ratio of output offset to true signal is increased.
The input to the n bit parallel analog/digital converter goes through its range of possible voltage levels in every sub-range as the analog input goes through its full dynamic range. Bias errors in the analog chain can produce saturation of the analog/digital converter in some sub-ranges for a given analog input. This produces discontinuities in the final analog/digital converter output. Accordingly, there currently exists the need for automatic bias correction circuits that obviate the adverse effects of the foregoing enumerated source of bias error. The present invention is directed toward satisfying that need.